Design of high-performance quaternary adders based on output-generator sharing

Hirokatsu Shirahama, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs). Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations. The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which improves the performance of the resulting quaternary full adders. For example, two kinds of single PEs including a quaternary full adder and two flip-flops are implemented using the proposed method and their efficiencies are demonstrated in terms of delay and power dissipation in comparison with those of a corresponding binary CMOS implementation.

Original languageEnglish
Title of host publicationProceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Pages8-13
Number of pages6
DOIs
Publication statusPublished - 2008 Sep 3
Event38th International Symposium on Multiple-Valued Logic, ISMVL 2008 - Dallas, TX, United States
Duration: 2008 May 222008 May 24

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other38th International Symposium on Multiple-Valued Logic, ISMVL 2008
CountryUnited States
CityDallas, TX
Period08/5/2208/5/24

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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