TY - JOUR

T1 - Design of frequency-mode set-valued logic networks

AU - Aoki, T.

AU - Yuminaka, Y.

AU - Higuchi, T.

PY - 1993/1/1

Y1 - 1993/1/1

N2 - A set-valued logic network is proposed to provide a potential solution to the interconnection problems in VLSI systems. The fundamental concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set-valued logic network can be constructed with two basic building blocks realized by frequency-selective circuits. A set-valued switching algebra is introduced for the systematic synthesis of networks. The set-valued logic network thus obtained has the attractive features of high information density, highly parallel structure and extensibility into ultra-higher-valued logic systems.

AB - A set-valued logic network is proposed to provide a potential solution to the interconnection problems in VLSI systems. The fundamental concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set-valued logic network can be constructed with two basic building blocks realized by frequency-selective circuits. A set-valued switching algebra is introduced for the systematic synthesis of networks. The set-valued logic network thus obtained has the attractive features of high information density, highly parallel structure and extensibility into ultra-higher-valued logic systems.

UR - http://www.scopus.com/inward/record.url?scp=0027614562&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027614562&partnerID=8YFLogxK

U2 - 10.1049/ip-g-2.1993.0031

DO - 10.1049/ip-g-2.1993.0031

M3 - Article

AN - SCOPUS:0027614562

VL - 140

SP - 191

EP - 198

JO - IET Circuits, Devices and Systems

JF - IET Circuits, Devices and Systems

SN - 1751-858X

IS - 3

ER -