### Abstract

A set-valued logic network is proposed to provide a potential solution to the interconnection problems in VLSI systems. The fundamental concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set-valued logic network can be constructed with two basic building blocks realized by frequency-selective circuits. A set-valued switching algebra is introduced for the systematic synthesis of networks. The set-valued logic network thus obtained has the attractive features of high information density, highly parallel structure and extensibility into ultra-higher-valued logic systems.

Original language | English |
---|---|

Pages (from-to) | 191-198 |

Number of pages | 8 |

Journal | IEE Proceedings, Part G: Circuits, Devices and Systems |

Volume | 140 |

Issue number | 3 |

DOIs | |

Publication status | Published - 1993 Jan 1 |

### ASJC Scopus subject areas

- Engineering(all)

## Fingerprint Dive into the research topics of 'Design of frequency-mode set-valued logic networks'. Together they form a unique fingerprint.

## Cite this

Aoki, T., Yuminaka, Y., & Higuchi, T. (1993). Design of frequency-mode set-valued logic networks.

*IEE Proceedings, Part G: Circuits, Devices and Systems*,*140*(3), 191-198. https://doi.org/10.1049/ip-g-2.1993.0031