Abstract
This paper designs and evaluates fine grain VLSI array processors for real-time 2-D state-space digital filters. The architecture of the VLSI array processors is a linear systolic array, of which processing elements (PEs) are simple and homogeneous 1-D state-space digital filters. The number of PEs are equal to the number of rows of the processing images. Hierarchical behavioral description language and synthesizer are utilized for the design and evaluation of the VLSI array processors. One VLSI chip is composed of 129 k gates and is integrated into one 14.70 × 14.98 mm2 VLSI chip using 1 μm CMOS technology. Eight PEs can be integrated into one VLSI chip. The fine grain VLSI array processors system composed of 128 designed VLSI chips at 25 MHz clock can process a 1,024 × 1,024 image in 1.47 msec and thus can be applied to real-time video signal processing.
| Original language | English |
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| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | Publ by IEEE |
| Pages | 1559-1562 |
| Number of pages | 4 |
| Volume | 3 |
| ISBN (Print) | 0780312813 |
| Publication status | Published - 1993 Jan 1 |
| Event | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: 1993 May 3 → 1993 May 6 |
Other
| Other | Proceedings of the 1993 IEEE International Symposium on Circuits and Systems |
|---|---|
| City | Chicago, IL, USA |
| Period | 93/5/3 → 93/5/6 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering