Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

Michitaka Kameyama; Tatsuo Higuchi

doi:10.1109/JSSC.1980.1051348

Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Microcomputer system reliability using triple-modulare. dundancy (TMR) is discussed when failures exist not only in any singfe module but also in any two or three modules at a time. The optimaf time intervaf is calculated by which the system wilf even be desynchronized periodically so that additional transient faitures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU'S.

Original language	English
Pages (from-to)	138-142
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	15
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.1980.1051348
Publication status	Published - 1980 Feb
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1980.1051348

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@article{afa98165abe049d787cfe7407da4e730,

title = "Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy",

abstract = "Microcomputer system reliability using triple-modulare. dundancy (TMR) is discussed when failures exist not only in any singfe module but also in any two or three modules at a time. The optimaf time intervaf is calculated by which the system wilf even be desynchronized periodically so that additional transient faitures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU'S.",

author = "Michitaka Kameyama and Tatsuo Higuchi",

year = "1980",

month = feb,

doi = "10.1109/JSSC.1980.1051348",

language = "English",

volume = "15",

pages = "138--142",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

AU - Kameyama, Michitaka

AU - Higuchi, Tatsuo

PY - 1980/2

Y1 - 1980/2

N2 - Microcomputer system reliability using triple-modulare. dundancy (TMR) is discussed when failures exist not only in any singfe module but also in any two or three modules at a time. The optimaf time intervaf is calculated by which the system wilf even be desynchronized periodically so that additional transient faitures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU'S.

AB - Microcomputer system reliability using triple-modulare. dundancy (TMR) is discussed when failures exist not only in any singfe module but also in any two or three modules at a time. The optimaf time intervaf is calculated by which the system wilf even be desynchronized periodically so that additional transient faitures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU'S.

UR - http://www.scopus.com/inward/record.url?scp=0018982770&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0018982770&partnerID=8YFLogxK

U2 - 10.1109/JSSC.1980.1051348

DO - 10.1109/JSSC.1980.1051348

M3 - Article

AN - SCOPUS:0018982770

VL - 15

SP - 138

EP - 142

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 1

ER -

Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

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