Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

Michitaka Kameyama; Tatsuo Higuchi

doi:10.1109/JSSC.1980.1051348

Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

Michitaka Kameyama, Tatsuo Higuchi

INF - Computer and Mathematical Sciences

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Microcomputer system reliability using triple-modulare. dundancy (TMR) is discussed when failures exist not only in any singfe module but also in any two or three modules at a time. The optimaf time intervaf is calculated by which the system wilf even be desynchronized periodically so that additional transient faitures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU'S.

Original language	English
Pages (from-to)	138-142
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	15
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.1980.1051348
Publication status	Published - 1980 Feb

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1980.1051348

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abstract = "Microcomputer system reliability using triple-modulare. dundancy (TMR) is discussed when failures exist not only in any singfe module but also in any two or three modules at a time. The optimaf time intervaf is calculated by which the system wilf even be desynchronized periodically so that additional transient faitures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU'S.",

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AB - Microcomputer system reliability using triple-modulare. dundancy (TMR) is discussed when failures exist not only in any singfe module but also in any two or three modules at a time. The optimaf time intervaf is calculated by which the system wilf even be desynchronized periodically so that additional transient faitures can be tolerated. It is shown that in spite of the optimal reaynchronisation, the reliability of the system cannot be improved by the ordinary TMR under some dependent-failures. For the purpose of eliminating the effect of dependent-failures, a new fault-tolerant microcomputer system is proposed where a program is executed three times by three CPU'S.

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Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

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