Design of an RSA Encryption Processor Based on Signed‐Digit Multivalued Arithmetic Circuits

Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This paper proposes an LSI‐oriented multiple‐valued hardware algorithm based on the signed‐digit number (SD number) for highspeed RSA public key encryption processor. A very long word‐length arithmetic is required in RSA encryption processing. The proposed algorithm realizes a high‐speed processing by iterative additions based on the radix‐A SD number system. Microprogram control is adopted in the encryption processor. To verify the basic operation of the proposed processor architecture, a model processor for 16‐bit encryption is implemented using binary TTL logic IC's. A comprehensive evaluation of the 2 μm CMOS encryption LSI is made by a simulation using the electronic circuit analysis program SPICE2. The encryption rate for the message of 512‐bit word length is 60 kbit/s, which is a factor of eight times faster than that of the corresponding binary LSI. The developed processor contains about 100 k transistors and it can be implemented on a single single chip.

Original languageEnglish
Pages (from-to)21-31
Number of pages11
JournalSystems and Computers in Japan
Volume21
Issue number6
DOIs
Publication statusPublished - 1990

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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