TY - GEN
T1 - Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure
AU - Suzuki, Daisuke
AU - Hanyu, Takahiro
PY - 2015/9/28
Y1 - 2015/9/28
N2 - A 6-input nonvolatile lookup table (LUT) circuit is proposed using an energy-efficient single-ended logic-in-memory (LIM) structure in conjunction with a magnetic tunnel junction (MTJ) device. While the use of a conventional single-ended LIM structure makes the multi-input LUT circuit compact, a long delay due to the small difference in the MTJ resistance and a large amount of dynamic power consumption due to a DC current path are unavoidable. To overcome the problem, a PMOS feedback transistor which makes it possible to accelerate the logic operation is utilized in the proposed LUT circuit. The use of the PMOS feedback transistor also makes it possible to reduce dynamic power consumption by automatically cutting off the DC current just after logic value '0' is read. In fact, the power-delay product of the proposed 6-input LUT circuit is reduced by 66% in comparison with that of the conventional single-ended one under a 90-nm CMOS technology.
AB - A 6-input nonvolatile lookup table (LUT) circuit is proposed using an energy-efficient single-ended logic-in-memory (LIM) structure in conjunction with a magnetic tunnel junction (MTJ) device. While the use of a conventional single-ended LIM structure makes the multi-input LUT circuit compact, a long delay due to the small difference in the MTJ resistance and a large amount of dynamic power consumption due to a DC current path are unavoidable. To overcome the problem, a PMOS feedback transistor which makes it possible to accelerate the logic operation is utilized in the proposed LUT circuit. The use of the PMOS feedback transistor also makes it possible to reduce dynamic power consumption by automatically cutting off the DC current just after logic value '0' is read. In fact, the power-delay product of the proposed 6-input LUT circuit is reduced by 66% in comparison with that of the conventional single-ended one under a 90-nm CMOS technology.
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U2 - 10.1109/MWSCAS.2015.7282195
DO - 10.1109/MWSCAS.2015.7282195
M3 - Conference contribution
AN - SCOPUS:84962109806
T3 - Midwest Symposium on Circuits and Systems
BT - IEEE 58th International Midwest Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015
Y2 - 2 August 2015 through 5 August 2015
ER -