Design of a two-bit-per-cell content-addressable memory using single-electron transistors

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hlroshi Lnokawa, Yasuo Takahashi

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

This paper presents a circuit design of a two-bit-per-cell ContentAddressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces both the number of transistors and the cell area to 1/3 compared with the conventional CAM architecture.

Original languageEnglish
Pages (from-to)249-266
Number of pages18
JournalJournal of Multiple-Valued Logic and Soft Computing
Volume13
Issue number3
Publication statusPublished - 2007 Nov 29

Keywords

  • Content-addressable memories
  • Single-electron transistors

ASJC Scopus subject areas

  • Logic

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