This paper presents a circuit design of a two-bit-per-cell ContentAddressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces both the number of transistors and the cell area to 1/3 compared with the conventional CAM architecture.
|Number of pages||18|
|Journal||Journal of Multiple-Valued Logic and Soft Computing|
|Publication status||Published - 2007 Nov 29|
- Content-addressable memories
- Single-electron transistors
ASJC Scopus subject areas