Design of a trinocular-stereo-vision vlsi processor based on optimal scheduling

This paper presents a processnr architecture for high- speed and reliable trinocular stereo matching based on adaptive window- size control of SAD (Sum of Absolute Differences) computation. To redoce its computational complexity, SADs are computed using images divided into nun-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on regularity of reference pixels. The stereo matching processor is designed in a 0.18 pm CMOS technology. The processing time is 83.2ps@ 100 MHz. By using optimal scheduling, the increases in area and processing time is only 5% and 3% respectively compared to binocular stereo vision although the com putational amount is double.