Abstract
This paper introduces a soft-error tolerant ternary content-addressable memory (TCAM) cell based on a transistor/magnetic-tunnel-junction (MTJ) hybrid structure. The MTJ device stores one-bit information as a resistance value and is often used for non-volatile memories. In the proposed nine-transistor (9T)/six-MTJ (6MTJ) cell, one-bit information is redundantly represented using three MTJs to mask a one-bit error per cell that might be occurred due to particle strikes. Thanks to the stackability of the MTJ device over a CMOS layer, there is no area overhead due to the redundancy compared to a conventional 9T-2MTJ cell. A 256-word 64-bit TCAM based on the proposed cell is designed under a 90nm CMOS/MTJ process and is evaluated using HSPICE simulation. The simulation results show that the proposed TCAM properly operates under a one-bit error per cell with comparable energy, area and a 14% delay overhead compared to the conventional TCAM. Compared to a CMOS-based TCAM with an error-correction code that masks a one-bit error per word, the proposed TCAM reduces the nubmer of transistors by 81% while masking a one-bit error per cell.
| Original language | English |
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| Title of host publication | 2014 IEEE 12th International New Circuits and Systems Conference, NEWCAS 2014 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 193-196 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781479948857 |
| DOIs | |
| Publication status | Published - 2014 Jan 1 |
| Event | 2014 12th IEEE International New Circuits and Systems Conference, NEWCAS 2014 - Trois-Rivieres, Canada Duration: 2014 Jun 22 → 2014 Jun 25 |
Other
| Other | 2014 12th IEEE International New Circuits and Systems Conference, NEWCAS 2014 |
|---|---|
| Country | Canada |
| City | Trois-Rivieres |
| Period | 14/6/22 → 14/6/25 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Control and Systems Engineering
- Computer Networks and Communications
- Software