Design of a set logic network based on frequency multiplexing and its applications to image processing

Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

An ultra-higher-valued logic network, called a set logic network, is proposed to provide a potential solution to the interconnection problems in VLSI systems. The basic concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set logic network can be constructed with only two basic building blocks realized by frequency-selective analog circuits. Its application to a parallel image processor is discussed based on functional multiplexing of binary modules into a single set logic module. A great reduction of interconnections can be achieved by using an optimal multiplexing scheme.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages8-15
Number of pages8
ISBN (Print)0818621451
Publication statusPublished - 1991 May 1
EventProceedings of the 21st International Symposium on Multiple-Valued Logic - Victoria, BC, Can
Duration: 1991 May 261991 May 29

Other

OtherProceedings of the 21st International Symposium on Multiple-Valued Logic
CityVictoria, BC, Can
Period91/5/2691/5/29

ASJC Scopus subject areas

  • Chemical Health and Safety
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Logic

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