Abstract
An ultra-higher-valued logic network, called a set logic network, is proposed to provide a potential solution to the interconnection problems in VLSI systems. The basic concept is frequency multiplexing of logic values for the increase of information density in logic networks. It is shown that the set logic network can be constructed with only two basic building blocks realized by frequency-selective analog circuits. Its application to a parallel image processor is discussed based on functional multiplexing of binary modules into a single set logic module. A great reduction of interconnections can be achieved by using an optimal multiplexing scheme.
| Original language | English |
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| Title of host publication | Proceedings of The International Symposium on Multiple-Valued Logic |
| Publisher | Publ by IEEE |
| Pages | 8-15 |
| Number of pages | 8 |
| ISBN (Print) | 0818621451 |
| Publication status | Published - 1991 May 1 |
| Event | Proceedings of the 21st International Symposium on Multiple-Valued Logic - Victoria, BC, Can Duration: 1991 May 26 → 1991 May 29 |
Other
| Other | Proceedings of the 21st International Symposium on Multiple-Valued Logic |
|---|---|
| City | Victoria, BC, Can |
| Period | 91/5/26 → 91/5/29 |
ASJC Scopus subject areas
- Chemical Health and Safety
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
- Logic