Design of a robust fault‐tolerant multiplier

Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a construction of a robust fault‐tolerant multiplier aiming at high safety, where the output does not differ much from the normal value, even if a temporary fault is produced in the operation unit. For this purpose, a robust fault‐tolerant divider circuit by a fixed positive constant is devised, which is called divider. The multiplier is constructed by arranging such dividers in parallel. The proposed robust fault‐tolerant multiplier is based on the distributed coding, where the input/output information is always represented by the number of pulses. Consequently, a system‐down is not produced even if more than one temporary error is generated, which is different from the majority redundant circuit. Another feature is that there is no hardware core, such as the majority‐decision circuit for the output signal selection, and a temporary error does not produce a system‐down.

Original languageEnglish
Pages (from-to)10-18
Number of pages9
JournalSystems and Computers in Japan
Volume22
Issue number2
DOIs
Publication statusPublished - 1991

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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