Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture

Yoshichika Fujioka, Michitaka Kameyama

Research output: Contribution to journalArticle

Abstract

In realization of intelligent robots with the capability of quick response to altering environments, it is necessary to reduce the operation delay time of the sensor input signal to the control output. In this article, dynamically reconfigurable multioperand multiplication-addition based on bit-serial operations on multiple inputs is proposed. As a consequence, not only the utilization of the full address provided in the computational section, but also those of the local memory, controller, and distribution lines inside the chip, can thoroughly be improved. The structure of the corresponding reconfigurable VLSI processor is also proposed. In reconfigurable VLSI processors, the overhead of data transfer between processing elements (PE) is remarkably decreased, resulting in the reduction of the product of the PE chip area and the multiplication-addition time (i.e., area-time product). Therefore, the overall computation capability of the processor is remarkably improved. For example, performance evaluation of the chip based on the 0.8-μm CMOS design rule showed that the delay time of multioperand multiplications-additions and the area-time product are reduced threefold, compared with those of reconfigurable VLSI processors based on bit-parallel architecture.

Original languageEnglish
Pages (from-to)43-51
Number of pages9
JournalSystems and Computers in Japan
Volume30
Issue number12
DOIs
Publication statusPublished - 1999 Nov 15

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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