Design of a reconfigurable parallel processor for digital control using FPGAs

In digital control, it is essential to make the delay time for a large number of multiply-additions small because of sensor feedback. To meet the requirement, an architecture of the reconfigurable parallel processor using field-programmable gate arrays (FPGAs) is proposed. Although the performance is drastically increased in the full custom VLSI implementation, even the reconfigurable parallel processor using FPGAs becomes useful for many practical digital control applications. The performance evaluation shows that the delay time for the resolved acceleration control computation of a twelve-degrees-of-freedom (DOF) redundant manipulator becomes about 70 μs which is about seventeen times faster than that of a parallel processor approach using conventional digital signal processors (DSPs).