TY - GEN
T1 - Design of a quaternary single-ended current-mode circuit for an energy-efficient inter-chip asynchronous communication link
AU - Mochizuki, Akira
AU - Shirahama, Hirokatsu
AU - Hanyu, Takahiro
PY - 2014/1/1
Y1 - 2014/1/1
N2 - A single-ended-style current-mode circuit with quaternary current signaling is proposed for an energy-efficient asynchronous communication link. The use of quaternary-encoded current signaling and dynamic current-feedback mechanism makes information density twice per wire because of small signal-voltage swing with maintaining high-speed switching capability, which resulting in energy-efficient asynchronous data transmission. It is demonstrated that the proposed link with a 10mm inter-chip transmission line achieves the throughput of 1.1Gbps per wire at the power supply of 1.2V under a 130nm CMOS technology.
AB - A single-ended-style current-mode circuit with quaternary current signaling is proposed for an energy-efficient asynchronous communication link. The use of quaternary-encoded current signaling and dynamic current-feedback mechanism makes information density twice per wire because of small signal-voltage swing with maintaining high-speed switching capability, which resulting in energy-efficient asynchronous data transmission. It is demonstrated that the proposed link with a 10mm inter-chip transmission line achieves the throughput of 1.1Gbps per wire at the power supply of 1.2V under a 130nm CMOS technology.
KW - NoC
KW - asynchronous communication link
KW - current-mode
KW - multiple-valued
KW - network on chip
UR - http://www.scopus.com/inward/record.url?scp=84904460823&partnerID=8YFLogxK
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U2 - 10.1109/ISMVL.2014.20
DO - 10.1109/ISMVL.2014.20
M3 - Conference contribution
AN - SCOPUS:84904460823
SN - 9781479935345
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 67
EP - 72
BT - Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014
PB - IEEE Computer Society
T2 - 44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
Y2 - 19 May 2014 through 21 May 2014
ER -