Abstract
A high-speed, low-power and compact processing element (PE) using quaternary differential logic is proposed for a multi-core single-instruction multiple-data (SIMD) processor. A two-bit addition which is the critical path of the ALU is attributed to a one-digit quaternary addition that is directly performed by using multiple-valued currentmode (MVCM) differential logic circuitry. A one-digit quaternary flip-flop is also simply implemented by using the MVCM differential logic circuitry. The efficiency of the proposed quaternary PE is demonstrated using 0.18μm CMOS HSPICE simulation in comparison with a corresponding CMOS implementation.
| Original language | English |
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| Title of host publication | 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 |
| DOIs | |
| Publication status | Published - 2007 Sep 3 |
| Event | 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway Duration: 2007 May 13 → 2007 May 16 |
Publication series
| Name | Proceedings of The International Symposium on Multiple-Valued Logic |
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| ISSN (Print) | 0195-623X |
Other
| Other | 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 |
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| Country | Norway |
| City | Oslo |
| Period | 07/5/13 → 07/5/16 |
ASJC Scopus subject areas
- Computer Science(all)
- Mathematics(all)
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Shirahama, H., Mochizuki, A., Hanyu, T., Nakajima, M., & Arimoto, K. (2007). Design of a processing element based on quaternary differential logic for a multi-core SIMD processor. In 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 [4215966] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2007.14