TY - GEN
T1 - Design of a processing element based on quaternary differential logic for a multi-core SIMD processor
AU - Shirahama, Hirokatsu
AU - Mochizuki, Akira
AU - Hanyu, Takahiro
AU - Nakajima, Masami
AU - Arimoto, Kazutami
PY - 2007/9/3
Y1 - 2007/9/3
N2 - A high-speed, low-power and compact processing element (PE) using quaternary differential logic is proposed for a multi-core single-instruction multiple-data (SIMD) processor. A two-bit addition which is the critical path of the ALU is attributed to a one-digit quaternary addition that is directly performed by using multiple-valued currentmode (MVCM) differential logic circuitry. A one-digit quaternary flip-flop is also simply implemented by using the MVCM differential logic circuitry. The efficiency of the proposed quaternary PE is demonstrated using 0.18μm CMOS HSPICE simulation in comparison with a corresponding CMOS implementation.
AB - A high-speed, low-power and compact processing element (PE) using quaternary differential logic is proposed for a multi-core single-instruction multiple-data (SIMD) processor. A two-bit addition which is the critical path of the ALU is attributed to a one-digit quaternary addition that is directly performed by using multiple-valued currentmode (MVCM) differential logic circuitry. A one-digit quaternary flip-flop is also simply implemented by using the MVCM differential logic circuitry. The efficiency of the proposed quaternary PE is demonstrated using 0.18μm CMOS HSPICE simulation in comparison with a corresponding CMOS implementation.
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U2 - 10.1109/ISMVL.2007.14
DO - 10.1109/ISMVL.2007.14
M3 - Conference contribution
AN - SCOPUS:34548207146
SN - 0769528317
SN - 9780769528311
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
BT - 37th International Symposium on Multiple-Valued Logic, ISMVL 2007
T2 - 37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Y2 - 13 May 2007 through 16 May 2007
ER -