Design of a Multiple‐Valued Associative Memory

Takahiro Hanyu, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review


Associative memories and associaLive computer systems with high‐speed processing capability have been increasingly required in the real‐time application domains, such as File Maintenance, Pattern Recognition, Translation, Artificial Intelligence, and so on. This paper presents a design of high‐performance multiple‐valued associative memory which can perform ultrahigh‐speed processing at low cost. In the proposed method, the correlation between input pattern and memorized pattern is represented directly as multiple‐valued information, so that associative processing is performed efficiently by multiple‐valued operations. Based on a complete parallel processing architecture with multiple‐valued digit‐cell, each correlation can be calculated in parallel. In hardware implementation of a single digit‐cell, two kinds of new devices are proposed: the SOS transistor and the floating‐gate MOS transistor. By using these devices, multiple‐valued operators and multiple‐valued memories for the associative memory can be realized efficiently at the device level. It is demonstrated that compared with the corresponding binary implementation the proposed associative memory is very compact.

Original languageEnglish
Pages (from-to)23-33
Number of pages11
JournalSystems and Computers in Japan
Issue number12
Publication statusPublished - 1989 Jan 1

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics


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