Design of a multiple-valued VLSI processor for digital control

Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A high-performance parallel, multivalued VLSI processor using the radix-2 signed-digit number system is proposed. Multivalued bidirectional current-mode technology is used not only in the high-speed small-sized arithmetic circuits, but also in reducing the number of connections. Compactness and high-speed operation enhance the performance of the processor chip under the chip size limitation. The processor has been developed for real-time digital control, where the performance is evaluated by delay time. A performance estimation using SPICE simulators shows that the delay time of the processor for operations such as matrix multiplication is greatly reduced in comparison to a conventional binary processor.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages322-329
Number of pages8
ISBN (Print)0818626801
Publication statusPublished - 1992 May 1
EventProceedings of the 22nd International Symposium on Multiple-Valued Logic - Sendai, Jpn
Duration: 1992 May 271992 May 29

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

OtherProceedings of the 22nd International Symposium on Multiple-Valued Logic
CitySendai, Jpn
Period92/5/2792/5/29

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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