Design of a multiple-valued rule-programmable matching VLSI chip for real-time rule-based systems

Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A multivalued VLSI processor design for fully parallel pattern matching is presented. It can be applied to real-time rule-based systems with large knowledge bases which are programmable. One-digit pattern matching based on direct multivalued encoding of each attribute can be described by only a programmable delta literal. Moreover, the literal circuit can be easily implemented using two floating-gate MOS devices whose threshold voltages are controllable. The inference time of an eight-valued matching processor with 256 rules and conflict resolution circuits is estimated at about 360 ns, and the chip area is reduced to about 10% of that of the equivalent binary implementation.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages274-281
Number of pages8
ISBN (Print)0818626801
Publication statusPublished - 1992 May 1
Externally publishedYes
EventProceedings of the 22nd International Symposium on Multiple-Valued Logic - Sendai, Jpn
Duration: 1992 May 271992 May 29

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

OtherProceedings of the 22nd International Symposium on Multiple-Valued Logic
CitySendai, Jpn
Period92/5/2792/5/29

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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