Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a novel asynchronous bitserial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed contextID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.

Original languageEnglish
Title of host publication2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC)
Subtitle of host publicationDesign, Applications, Integration, and Software, DCAS-07
Pages59-62
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07 - Dallas, TX, United States
Duration: 2007 Nov 152007 Nov 16

Publication series

Name2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07

Other

Other2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07
CountryUnited States
CityDallas, TX
Period07/11/1507/11/16

Keywords

  • Dynamically reconfigurable
  • FPGA
  • Self timing

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software
  • Electrical and Electronic Engineering

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