Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture

Waidyasooriya Hasitha Muthumala; Masanori Hariyama; Michitaka Kameyama

doi:10.1109/DCAS.2007.4433216

Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture

Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a novel asynchronous bitserial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed contextID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.

Original language	English
Title of host publication	2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC)
Subtitle of host publication	Design, Applications, Integration, and Software, DCAS-07
Pages	59-62
Number of pages	4
DOIs	https://doi.org/10.1109/DCAS.2007.4433216
Publication status	Published - 2007 Dec 1
Event	2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07 - Dallas, TX, United States Duration: 2007 Nov 15 → 2007 Nov 16

Publication series

Name	2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07

Other

Other	2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07
Country/Territory	United States
City	Dallas, TX
Period	07/11/15 → 07/11/16

Keywords

Dynamically reconfigurable
FPGA
Self timing

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Computer Science Applications
Software
Electrical and Electronic Engineering

Access to Document

10.1109/DCAS.2007.4433216

Cite this

Muthumala, W. H., Hariyama, M., & Kameyama, M. (2007). Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture. In 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07 (pp. 59-62). [4433216] (2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07). https://doi.org/10.1109/DCAS.2007.4433216

Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture. / Muthumala, Waidyasooriya Hasitha ; Hariyama, Masanori; Kameyama, Michitaka.

2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07. 2007. p. 59-62 4433216 (2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Muthumala, WH , Hariyama, M & Kameyama, M 2007, Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture. in 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07., 4433216, 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07, pp. 59-62, 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07, Dallas, TX, United States, 07/11/15. https://doi.org/10.1109/DCAS.2007.4433216

Muthumala WH , Hariyama M, Kameyama M. Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture. In 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07. 2007. p. 59-62. 4433216. (2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07). doi: 10.1109/DCAS.2007.4433216

Muthumala, Waidyasooriya Hasitha ; Hariyama, Masanori ; Kameyama, Michitaka. / Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture. 2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07. 2007. pp. 59-62 (2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07).

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abstract = "This paper presents a novel asynchronous bitserial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed contextID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.",

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N2 - This paper presents a novel asynchronous bitserial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed contextID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.

AB - This paper presents a novel asynchronous bitserial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed contextID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.

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Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture

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