Design of a multi-context FPGA using a floating-gate-MOS functional pass-gate

Masanori Hariyama, Sho Ogata, Michitaka Kameyama, Yasutoshi Morita

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate(FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The transistor count of the proposed multi-context switch (MC-swltch) is reduced to 10% in comparison with SRAM-based one. The transistor count of the proposed MC-switch is also reduced to 20% in comparison with the MC-switch that uses floating-gate MOS transistors just as storage device. The test chip is designed using a 0.35μm EPROM technology, and the area of the proposed MC-FPGA is reduced to about 50% of that of a conventional MC-FPGA.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PublisherIEEE Computer Society
Pages421-424
Number of pages4
ISBN (Print)0780391624, 9780780391628
DOIs
Publication statusPublished - 2005 Jan 1
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China
Duration: 2005 Nov 12005 Nov 3

Publication series

Name2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Other

Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan, Province of China
CityHsinchu
Period05/11/105/11/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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