Design of a massively parallel vision processor based on multi-SIMD rchitecture

Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)

Abstract

Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to handle highly complicated recognition tasks. We describe a multi-SIMD architecture and the design of a vision processor based on it for carrying out such difficult image recognition tasks. The proposed architecture consists of two SIMD parallel processing modules and a shared memory, allowing highly parallelized and flexible computation of complicated recognition tasks, which were difficult to process on a conventional massively parallel SIMD architecture. We designed a prototype vision processor for evaluation purposes and confirmed that the processor could be implemented in FPGA.

Original languageEnglish
Article number4253434
Pages (from-to)3498-3501
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2007 Sep 27
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 2007 May 272007 May 30

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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