A new multiple-valued current-mode integrated circuit based on dynamic source-coupled logic is proposed for a low-power arithmetic- oriented VLSI processor. A judicious combination of source-coupled logic and dynamic logic makes it possible to reduce the power dissipation while maintaining a high-speed switching capability because the dynamic logic style makes steady current flow cut off. As a typical example of a high-performance arithmetic circuit, a radix-2 signed-digit full adder based on the dynamic source-coupled logic is implemented using a 0.18μm CMOS technology. Its power dissipation is reduced to about 70 percent in comparison with that of a corresponding binary CMOS implementation.
|Number of pages||17|
|Journal||Journal of Multiple-Valued Logic and Soft Computing|
|Publication status||Published - 2005 Aug 15|
ASJC Scopus subject areas
- Theoretical Computer Science