Design of a low-energy nonvolatile fully-parallel ternary CAM using a two-level segmented match-line scheme

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A novel compact and static-power-free nonvolatile ternary content-addressable memory (TCAM) cell, where two-bit nonvolatile magnetic tunnel junction (MTJ) devices are stacked over the comparison logic circuit, is proposed for a high-density and ultra low-energy fully-parallel TCAM. The use of nonvolatile logic-in-memory circuit architecture makes it possible to realize 6T-2MTJ TCAM cell structure. The 144-bit word match-line is divided into two parts (first 10-bit and last 134-bit parts), which greatly reduces the dynamic power dissipation with small overhead of the switching delay. In fact, it is evaluated by the HSPICE simulation under a 90nm CMOS/MTJ technology that the search energy (power-delay product) of the proposed TCAM is reduced to 16 percent in comparison with that of a nonvolatile TCAM without using a segmented match-line scheme.

Original languageEnglish
Title of host publicationProceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011
Pages99-104
Number of pages6
DOIs
Publication statusPublished - 2011 Aug 18
Event41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 - Tuusula, Finland
Duration: 2011 May 232011 May 25

Publication series

NameProceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011

Other

Other41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011
Country/TerritoryFinland
CityTuusula
Period11/5/2311/5/25

Keywords

  • Diode-Connected Transistor
  • Logic-in-Memory
  • Low-Power
  • MOS/MTJ-hybrid
  • Magnetic Tunnel Junction (MTJ)
  • Pass Transistor
  • Power-Delay Product
  • Search Energy
  • Spintronics

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Applied Mathematics

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