@inproceedings{87ad4db7f13d4b04b2ddcf1bf9cfa655,
title = "Design of a low-energy nonvolatile fully-parallel ternary CAM using a two-level segmented match-line scheme",
abstract = "A novel compact and static-power-free nonvolatile ternary content-addressable memory (TCAM) cell, where two-bit nonvolatile magnetic tunnel junction (MTJ) devices are stacked over the comparison logic circuit, is proposed for a high-density and ultra low-energy fully-parallel TCAM. The use of nonvolatile logic-in-memory circuit architecture makes it possible to realize 6T-2MTJ TCAM cell structure. The 144-bit word match-line is divided into two parts (first 10-bit and last 134-bit parts), which greatly reduces the dynamic power dissipation with small overhead of the switching delay. In fact, it is evaluated by the HSPICE simulation under a 90nm CMOS/MTJ technology that the search energy (power-delay product) of the proposed TCAM is reduced to 16 percent in comparison with that of a nonvolatile TCAM without using a segmented match-line scheme.",
keywords = "Diode-Connected Transistor, Logic-in-Memory, Low-Power, MOS/MTJ-hybrid, Magnetic Tunnel Junction (MTJ), Pass Transistor, Power-Delay Product, Search Energy, Spintronics",
author = "Shoun Matsunaga and Akira Katsumata and Masanori Natsui and Takahiro Hanyu",
year = "2011",
month = aug,
day = "18",
doi = "10.1109/ISMVL.2011.41",
language = "English",
isbn = "9780769544052",
series = "Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011",
pages = "99--104",
booktitle = "Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011",
note = "41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 ; Conference date: 23-05-2011 Through 25-05-2011",
}