Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme

Shintaro Harada; Xu Bai; Michitaka Kameyama; Yoshichika Fujioka

doi:10.1109/ISMVL.2014.45

Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme

Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A new packet data transfer scheme (PDTS) is introduced to reduce a configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the CCM size for memory access is proportional not to the number of distributed memory modules in the reconfigurable VLSI, but to the number of read operations in all the memories. Thus, remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain ON/OFF control of the current sources in Differential-Pair Circuits (DPCs) utilizing flag information which indicates whether the data is valid or invalid.

Original language	English
Title of host publication	Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014
Publisher	IEEE Computer Society
Pages	214-219
Number of pages	6
ISBN (Print)	9781479935345
DOIs	https://doi.org/10.1109/ISMVL.2014.45
Publication status	Published - 2014
Event	44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014 - Bremen, Germany Duration: 2014 May 19 → 2014 May 21

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
Country	Germany
City	Bremen
Period	14/5/19 → 14/5/21

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Access to Document

10.1109/ISMVL.2014.45

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Harada, S., Bai, X., Kameyama, M., & Fujioka, Y. (2014). Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme. In Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014 (pp. 214-219). [6845023] (Proceedings of The International Symposium on Multiple-Valued Logic). IEEE Computer Society. https://doi.org/10.1109/ISMVL.2014.45

Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme. / Harada, Shintaro; Bai, Xu; Kameyama, Michitaka; Fujioka, Yoshichika.

Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014. IEEE Computer Society, 2014. p. 214-219 6845023 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Harada, S, Bai, X, Kameyama, M & Fujioka, Y 2014, Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme. in Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014., 6845023, Proceedings of The International Symposium on Multiple-Valued Logic, IEEE Computer Society, pp. 214-219, 44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014, Bremen, Germany, 14/5/19. https://doi.org/10.1109/ISMVL.2014.45

Harada S, Bai X, Kameyama M, Fujioka Y. Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme. In Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014. IEEE Computer Society. 2014. p. 214-219. 6845023. (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2014.45

Harada, Shintaro ; Bai, Xu ; Kameyama, Michitaka ; Fujioka, Yoshichika. / Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme. Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014. IEEE Computer Society, 2014. pp. 214-219 (Proceedings of The International Symposium on Multiple-Valued Logic).

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Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme

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