TY - GEN
T1 - Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme
AU - Harada, Shintaro
AU - Bai, Xu
AU - Kameyama, Michitaka
AU - Fujioka, Yoshichika
PY - 2014
Y1 - 2014
N2 - A new packet data transfer scheme (PDTS) is introduced to reduce a configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the CCM size for memory access is proportional not to the number of distributed memory modules in the reconfigurable VLSI, but to the number of read operations in all the memories. Thus, remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain ON/OFF control of the current sources in Differential-Pair Circuits (DPCs) utilizing flag information which indicates whether the data is valid or invalid.
AB - A new packet data transfer scheme (PDTS) is introduced to reduce a configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the CCM size for memory access is proportional not to the number of distributed memory modules in the reconfigurable VLSI, but to the number of read operations in all the memories. Thus, remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain ON/OFF control of the current sources in Differential-Pair Circuits (DPCs) utilizing flag information which indicates whether the data is valid or invalid.
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U2 - 10.1109/ISMVL.2014.45
DO - 10.1109/ISMVL.2014.45
M3 - Conference contribution
AN - SCOPUS:84904459522
SN - 9781479935345
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 214
EP - 219
BT - Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014
PB - IEEE Computer Society
T2 - 44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
Y2 - 19 May 2014 through 21 May 2014
ER -