Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme

Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A new packet data transfer scheme (PDTS) is introduced to reduce a configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the CCM size for memory access is proportional not to the number of distributed memory modules in the reconfigurable VLSI, but to the number of read operations in all the memories. Thus, remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain ON/OFF control of the current sources in Differential-Pair Circuits (DPCs) utilizing flag information which indicates whether the data is valid or invalid.

Original languageEnglish
Title of host publicationProceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014
PublisherIEEE Computer Society
Pages214-219
Number of pages6
ISBN (Print)9781479935345
DOIs
Publication statusPublished - 2014 Jan 1
Event44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014 - Bremen, Germany
Duration: 2014 May 192014 May 21

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
CountryGermany
CityBremen
Period14/5/1914/5/21

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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  • Cite this

    Harada, S., Bai, X., Kameyama, M., & Fujioka, Y. (2014). Design of a logic-in-memory multiple-valued reconfigurable VLSI based on a bit-serial packet data transfer scheme. In Proceedings - 2014 IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014 (pp. 214-219). [6845023] (Proceedings of The International Symposium on Multiple-Valued Logic). IEEE Computer Society. https://doi.org/10.1109/ISMVL.2014.45