TY - JOUR
T1 - Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure
AU - Suzuki, Daisuke
AU - Hanyu, Takahiro
N1 - Publisher Copyright:
© 2019 The Japan Society of Applied Physics.
PY - 2019
Y1 - 2019
N2 - A magnetic tunnel junction-based lookup table (LUT) circuit based on the fractured logic-in-memory structure, which can operate one multi-input LUT circuit as well as several LUT circuits with a smaller number of inputs with a compact circuitry, is proposed. Since a complex NMOS tree for performing a combinational logic function is separated from a read-current path, the resistance of the series-connected NMOS transistors is greatly reduced, which makes it possible to enhance the read margin and to reduce the circuit delay. The read margin can also be improved by increasing the gate widths of the NMOS transistors that are shared among several memory cells with a small area overhead. In fact, the read margin of the proposed six-input LUT circuits is 30.9% higher compared with that of a conventional circuitry. The circuit delay of the proposed 6-input LUT circuit is 69% smaller the that of the conventional circuitry.
AB - A magnetic tunnel junction-based lookup table (LUT) circuit based on the fractured logic-in-memory structure, which can operate one multi-input LUT circuit as well as several LUT circuits with a smaller number of inputs with a compact circuitry, is proposed. Since a complex NMOS tree for performing a combinational logic function is separated from a read-current path, the resistance of the series-connected NMOS transistors is greatly reduced, which makes it possible to enhance the read margin and to reduce the circuit delay. The read margin can also be improved by increasing the gate widths of the NMOS transistors that are shared among several memory cells with a small area overhead. In fact, the read margin of the proposed six-input LUT circuits is 30.9% higher compared with that of a conventional circuitry. The circuit delay of the proposed 6-input LUT circuit is 69% smaller the that of the conventional circuitry.
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U2 - 10.7567/1347-4065/aafd98
DO - 10.7567/1347-4065/aafd98
M3 - Article
AN - SCOPUS:85065491242
VL - 58
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - SB
M1 - SBBB10
ER -