Design of a highly parallel multiple-valued linear digital system for k-ary operations based on extended representation matrices

Morihiro Ryu, Michitaka Kameyama

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)

Abstract

Design of highly parallel multiple-valued circuits for k-ary operations with minimum critical path delay is discussed. The linear circuit for a k-ary operation can be designed by superposition of k unary operations. The code assignment of the symbols must be consistent in all the unary operations. Moreover, a set of the sparse representation matrices must be found to make the circuit parallel. In this paper, a new design method is proposed based on the extended representation matrices having the same degree of sparseness with the companion matrices. As a fundamental of a general case, the k-ary operations composed of non-permutation unary operations are discussed. In the non-permutation circuit, the output digit is connected with either of a constant or an input digit. The determination of the directly connected digits based on the concepts of 'successor' and 'predecessor' is effectively employed for the consistent code assignment in the decomposed unary operations.

Original languageEnglish
Pages (from-to)20-25
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 1995 Jan 1
EventProceedings of the 1995 25th International Symposium on Multiple-Valued Logic - Bloomington, IN, USA
Duration: 1995 May 231995 May 25

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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