Design of a highly parallel ai processor using new multiple-valued MOS devices.

Takahiro Hanyu, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

A design for a highly parallel processor for real-time reasoning in artificial intelligence (AI) is presented. Knowledge is represented by an associative network based on multiple-valued logic, so that an universal representation can be achieved by varying the parameters between nodes. High-speed reasoning can be attributed to the parallel graph-search technique on this associative network. For its direct implementation, special MOS devices with threshold voltages that are controllable by the external input signals are used. For the four-valued associative network, it is demonstrated that the number of memory cells, cell interconnections, and transistors can be greatly reduced in comparison with the corresponding binary implementation.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages300-306
Number of pages7
ISBN (Print)0818608595
Publication statusPublished - 1988 Dec 1

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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