Design of a fine-grain reconfigurable VLSI based on logic-in-control architecture

Nobuaki Okada, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed to make interconnections between arithmetic/logic circuits and control circuits simple. Hybrid programming scheme based on wired programming and dynamic data-path control programming is introduced to achieve high utilization ratio of hardware resources. In logic-in-control architecture, the control circuit constructed by using multiple logic blocks can be provided near the arithmetic/logic circuit, which leads to small propagation delay of control signals. To reduce the complexity of interconnections between logic blocks in the control circuit, only one state in a state transition diagram is allocated to one logic block. Moreover, a logic block useful for implementing both of the arithmetic/logic circuit and the control circuit is designed by using a multiple-valued current-mode logic circuit.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages278-281
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: 2009 Nov 222009 Nov 24

Publication series

Name2009 International SoC Design Conference, ISOCC 2009

Other

Other2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period09/11/2209/11/24

Keywords

  • Direct allocation of a control/data flow graph
  • FPGA
  • Multiple-valued current-mode logic
  • Sequential logic circuit
  • Universal literal

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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