TY - GEN
T1 - Design of a fine-grain reconfigurable VLSI based on logic-in-control architecture
AU - Okada, Nobuaki
AU - Kameyama, Michitaka
PY - 2009/12/1
Y1 - 2009/12/1
N2 - A multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed to make interconnections between arithmetic/logic circuits and control circuits simple. Hybrid programming scheme based on wired programming and dynamic data-path control programming is introduced to achieve high utilization ratio of hardware resources. In logic-in-control architecture, the control circuit constructed by using multiple logic blocks can be provided near the arithmetic/logic circuit, which leads to small propagation delay of control signals. To reduce the complexity of interconnections between logic blocks in the control circuit, only one state in a state transition diagram is allocated to one logic block. Moreover, a logic block useful for implementing both of the arithmetic/logic circuit and the control circuit is designed by using a multiple-valued current-mode logic circuit.
AB - A multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed to make interconnections between arithmetic/logic circuits and control circuits simple. Hybrid programming scheme based on wired programming and dynamic data-path control programming is introduced to achieve high utilization ratio of hardware resources. In logic-in-control architecture, the control circuit constructed by using multiple logic blocks can be provided near the arithmetic/logic circuit, which leads to small propagation delay of control signals. To reduce the complexity of interconnections between logic blocks in the control circuit, only one state in a state transition diagram is allocated to one logic block. Moreover, a logic block useful for implementing both of the arithmetic/logic circuit and the control circuit is designed by using a multiple-valued current-mode logic circuit.
KW - Direct allocation of a control/data flow graph
KW - FPGA
KW - Multiple-valued current-mode logic
KW - Sequential logic circuit
KW - Universal literal
UR - http://www.scopus.com/inward/record.url?scp=77951484267&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77951484267&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2009.5423802
DO - 10.1109/SOCDC.2009.5423802
M3 - Conference contribution
AN - SCOPUS:77951484267
SN - 9781424450343
T3 - 2009 International SoC Design Conference, ISOCC 2009
SP - 278
EP - 281
BT - 2009 International SoC Design Conference, ISOCC 2009
T2 - 2009 International SoC Design Conference, ISOCC 2009
Y2 - 22 November 2009 through 24 November 2009
ER -