Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)

Abstract

This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circuit technology on the reduction of hardware complexity required for DSP-oriented programmable ICs. The prototype FPDF fabrication with 0.6,μm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 71%, respectively, compared with the standard binary logic implementation.

Original languageEnglish
Pages (from-to)2001-2010
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE86-A
Issue number8
Publication statusPublished - 2003 Aug

Keywords

  • FIR filters
  • FPGAs
  • Multiple-valued logic
  • Signal processor

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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