DESIGN OF A COMPLEMENTARY PASS GATE NETWORK FOR A MULTIPLE-VALUED LOGIC SYSTEM.

Kyu Ik Sohng, Michitaka Kameyama, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A complementary pass gate (CP-gate) is proposed as a basic building block for a multiple-valued logic system. A CP-gate composed of two pass transistors and a down literal circuit realized with multiple-level ion implants has features of high density, low power dissipation, symmetry, and extensibility into an arbitrary multiple-valued logic system. An optimal network synthesis technique is also presented for a quaternary logic system with a minimized number of CP-gates.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherIEEE
Pages142-149
Number of pages8
ISBN (Print)0818607750
Publication statusPublished - 1987 Jan 1

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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    Sohng, K. I., Kameyama, M., & Higuchi, T. (1987). DESIGN OF A COMPLEMENTARY PASS GATE NETWORK FOR A MULTIPLE-VALUED LOGIC SYSTEM. In Proceedings of The International Symposium on Multiple-Valued Logic (pp. 142-149). (Proceedings of The International Symposium on Multiple-Valued Logic). IEEE.