Abstract
A complementary pass gate (CP-gate) is proposed as a basic building block for a multiple-valued logic system. A CP-gate composed of two pass transistors and a down literal circuit realized with multiple-level ion implants has features of high density, low power dissipation, symmetry, and extensibility into an arbitrary multiple-valued logic system. An optimal network synthesis technique is also presented for a quaternary logic system with a minimized number of CP-gates.
Original language | English |
---|---|
Title of host publication | Proceedings of The International Symposium on Multiple-Valued Logic |
Publisher | IEEE |
Pages | 142-149 |
Number of pages | 8 |
ISBN (Print) | 0818607750 |
Publication status | Published - 1987 Jan 1 |
Publication series
Name | Proceedings of The International Symposium on Multiple-Valued Logic |
---|---|
ISSN (Print) | 0195-623X |
ASJC Scopus subject areas
- Computer Science(all)
- Mathematics(all)