This paper presents the design of a new high-performance VLSI processor based on a systematic methodology for area minimization under a time constraint. A VLSI-oriented algorithm based on regular iterations of coordinate transformation and matching operation are introduced. The VLSI-processor consists of several identical clusters which has a CAM for parallel matching operation and PEs for parallel coordinate transformation. Under a condition of 100% utilization of PEs and a CAM, area minimization of the VLSI-processor is attributed to minimization of area-time products of a CAM and a PE. A multiport CAM (MCAM) and a PE based on bit-serial pipelined architecture can be efficiently employed for the minimization. The result shows that the total area can be reduced by about 30% in comparison with a straightforward design and that the performance is several ten thousand times higher than that of a general-purpose processor.