Design of a collision detection VLSI processor based on minimization of area-time products

M. Hariyama, M. Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper presents the design of a new high-performance VLSI processor based on a systematic methodology for area minimization under a time constraint. A VLSI-oriented algorithm based on regular iterations of coordinate transformation and matching operation are introduced. The VLSI-processor consists of several identical clusters which has a CAM for parallel matching operation and PEs for parallel coordinate transformation. Under a condition of 100% utilization of PEs and a CAM, area minimization of the VLSI-processor is attributed to minimization of area-time products of a CAM and a PE. A multiport CAM (MCAM) and a PE based on bit-serial pipelined architecture can be efficiently employed for the minimization. The result shows that the total area can be reduced by about 30% in comparison with a straightforward design and that the performance is several ten thousand times higher than that of a general-purpose processor.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Robotics and Automation
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3691-3696
Number of pages6
ISBN (Print)078034300X
DOIs
Publication statusPublished - 1998 Jan 1
Event15th IEEE International Conference on Robotics and Automation, ICRA 1998 - Leuven, Belgium
Duration: 1998 May 161998 May 20

Publication series

NameProceedings - IEEE International Conference on Robotics and Automation
Volume4
ISSN (Print)1050-4729

Other

Other15th IEEE International Conference on Robotics and Automation, ICRA 1998
CountryBelgium
CityLeuven
Period98/5/1698/5/20

ASJC Scopus subject areas

  • Software
  • Control and Systems Engineering
  • Artificial Intelligence
  • Electrical and Electronic Engineering

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