Design of a 3-D stacked floating-point Goldschmidt divider

Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.

Original languageEnglish
Title of host publication2015 International 3D Systems Integration Conference, 3DIC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesTS8.28.1-TS8.28.4
ISBN (Electronic)9781467393850
DOIs
Publication statusPublished - 2015 Nov 20
EventInternational 3D Systems Integration Conference, 3DIC 2015 - Sendai, Japan
Duration: 2015 Aug 312015 Sep 2

Publication series

Name2015 International 3D Systems Integration Conference, 3DIC 2015

Other

OtherInternational 3D Systems Integration Conference, 3DIC 2015
CountryJapan
CitySendai
Period15/8/3115/9/2

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Design of a 3-D stacked floating-point Goldschmidt divider'. Together they form a unique fingerprint.

Cite this