Design impacts on NAND Flash memory core circuits with vertical MOSFETs

Koji Sakui; Tetsuo Endoh

doi:10.1109/IMW.2010.5488310

Design impacts on NAND Flash memory core circuits with vertical MOSFETs

Koji Sakui, Tetsuo Endoh

ENG - Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

By utilizing the vertical MOSFETs advantages, the compact, efficient, and low-power peripheral core circuit design for the NAND Flash memory has been proposed.

Original language	English
Title of host publication	2010 IEEE International Memory Workshop, IMW 2010
DOIs	https://doi.org/10.1109/IMW.2010.5488310
Publication status	Published - 2010 Oct 20
Event	2010 IEEE International Memory Workshop, IMW 2010 - Seoul, Korea, Republic of Duration: 2010 May 16 → 2010 May 19

Publication series

Name	2010 IEEE International Memory Workshop, IMW 2010

Other

Other	2010 IEEE International Memory Workshop, IMW 2010
Country/Territory	Korea, Republic of
City	Seoul
Period	10/5/16 → 10/5/19

ASJC Scopus subject areas

Hardware and Architecture

Access to Document

10.1109/IMW.2010.5488310

Cite this

@inproceedings{9605294e282b40c7b115797fe20dc381,

title = "Design impacts on NAND Flash memory core circuits with vertical MOSFETs",

abstract = "By utilizing the vertical MOSFETs advantages, the compact, efficient, and low-power peripheral core circuit design for the NAND Flash memory has been proposed.",

author = "Koji Sakui and Tetsuo Endoh",

year = "2010",

month = oct,

day = "20",

doi = "10.1109/IMW.2010.5488310",

language = "English",

isbn = "9781424467211",

series = "2010 IEEE International Memory Workshop, IMW 2010",

booktitle = "2010 IEEE International Memory Workshop, IMW 2010",

note = "2010 IEEE International Memory Workshop, IMW 2010 ; Conference date: 16-05-2010 Through 19-05-2010",

}

TY - GEN

T1 - Design impacts on NAND Flash memory core circuits with vertical MOSFETs

AU - Sakui, Koji

AU - Endoh, Tetsuo

PY - 2010/10/20

Y1 - 2010/10/20

N2 - By utilizing the vertical MOSFETs advantages, the compact, efficient, and low-power peripheral core circuit design for the NAND Flash memory has been proposed.

AB - By utilizing the vertical MOSFETs advantages, the compact, efficient, and low-power peripheral core circuit design for the NAND Flash memory has been proposed.

UR - http://www.scopus.com/inward/record.url?scp=77957901524&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77957901524&partnerID=8YFLogxK

U2 - 10.1109/IMW.2010.5488310

DO - 10.1109/IMW.2010.5488310

M3 - Conference contribution

AN - SCOPUS:77957901524

SN - 9781424467211

T3 - 2010 IEEE International Memory Workshop, IMW 2010

BT - 2010 IEEE International Memory Workshop, IMW 2010

T2 - 2010 IEEE International Memory Workshop, IMW 2010

Y2 - 16 May 2010 through 19 May 2010

ER -

Design impacts on NAND Flash memory core circuits with vertical MOSFETs

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this