Design and verification of parallel multipliers using arithmetic description language: ARITH

Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalConference article

6 Citations (Scopus)

Abstract

This paper proposes the basic concept of arithmetic description language called ARITH. The use of ARITH makes possible (i) formal description of arithmetic algorithms including those using unconventional number systems, (ii) formal verification of described arithmetic algorithms, and (iii) translation of arithmetic algorithms to equivalent HDL codes. In this paper, we demonstrate the potential of ARITH through an experimental design of parallel multipliers using binary signed-digit number system.

Original languageEnglish
Pages (from-to)334-339
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2004 Jul 26
EventProceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada
Duration: 2004 May 192004 May 22

ASJC Scopus subject areas

  • Hardware and Architecture
  • Logic
  • Safety, Risk, Reliability and Quality
  • Chemical Health and Safety

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