Abstract
This paper proposes the basic concept of arithmetic description language called ARITH. The use of ARITH makes possible (i) formal description of arithmetic algorithms including those using unconventional number systems, (ii) formal verification of described arithmetic algorithms, and (iii) translation of arithmetic algorithms to equivalent HDL codes. In this paper, we demonstrate the potential of ARITH through an experimental design of parallel multipliers using binary signed-digit number system.
| Original language | English |
|---|---|
| Pages (from-to) | 334-339 |
| Number of pages | 6 |
| Journal | Proceedings of The International Symposium on Multiple-Valued Logic |
| Publication status | Published - 2004 Jul 26 |
| Event | Proceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada Duration: 2004 May 19 → 2004 May 22 |
ASJC Scopus subject areas
- Hardware and Architecture
- Logic
- Safety, Risk, Reliability and Quality
- Chemical Health and Safety
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Ishida, K., Homma, N., Aoki, T., & Higuchi, T. (2004). Design and verification of parallel multipliers using arithmetic description language: ARITH. Proceedings of The International Symposium on Multiple-Valued Logic, 334-339.