Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell

Y. Asao, T. Kajiyama, Y. Fukuzumi, M. Amano, H. Aikawa, T. Ueda, T. Kishi, S. Ikegawa, K. Tsuchida, Y. Iwata, A. Nitayama, K. Shimura, Y. Kato, S. Miura, N. Ishiwata, H. Hada, S. Tahara, H. Yoda

Research output: Contribution to journalConference articlepeer-review

14 Citations (Scopus)

Abstract

A new cross point (CP) cell with a hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) (1). The new CP cell has a potential high density of 6F2 and a faster access time than the conventional CP cell. A cell layout design to realize 6F2 is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 μm CMOS technology and 0.24×0.48 μm2 magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

Original languageEnglish
Pages (from-to)571-574
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
Publication statusPublished - 2004 Dec 1
EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
Duration: 2004 Dec 132004 Dec 15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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