TY - GEN
T1 - Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices
AU - Shuto, Y.
AU - Yamamoto, S.
AU - Sukegawa, H.
AU - Wen, Z. C.
AU - Nakane, R.
AU - Mitani, S.
AU - Tanaka, M.
AU - Inomata, K.
AU - Sugahara, S.
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2012
Y1 - 2012
N2 - The design and performance of pseudo-spin-MOSFETs (PS-MOSFETs) using nano-CMOS devices were computationally investigated. The operations of a PS-MOSFET with current-induced magnetization switching were also experimentally demonstrated by the hybrid integration of a vendor-made MOSFET and our-developed spin-transfer-torque magnetic tunnel junction. The nonvolatile SRAM and delay flip-flop applications of PS-MOSFETs were also examined.
AB - The design and performance of pseudo-spin-MOSFETs (PS-MOSFETs) using nano-CMOS devices were computationally investigated. The operations of a PS-MOSFET with current-induced magnetization switching were also experimentally demonstrated by the hybrid integration of a vendor-made MOSFET and our-developed spin-transfer-torque magnetic tunnel junction. The nonvolatile SRAM and delay flip-flop applications of PS-MOSFETs were also examined.
UR - http://www.scopus.com/inward/record.url?scp=84876099996&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876099996&partnerID=8YFLogxK
U2 - 10.1109/IEDM.2012.6479131
DO - 10.1109/IEDM.2012.6479131
M3 - Conference contribution
AN - SCOPUS:84876099996
SN - 9781467348706
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 29.6.1-29.6.4
BT - 2012 IEEE International Electron Devices Meeting, IEDM 2012
T2 - 2012 IEEE International Electron Devices Meeting, IEDM 2012
Y2 - 10 December 2012 through 13 December 2012
ER -