Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices

Y. Shuto, S. Yamamoto, H. Sukegawa, Z. C. Wen, R. Nakane, S. Mitani, M. Tanaka, K. Inomata, S. Sugahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The design and performance of pseudo-spin-MOSFETs (PS-MOSFETs) using nano-CMOS devices were computationally investigated. The operations of a PS-MOSFET with current-induced magnetization switching were also experimentally demonstrated by the hybrid integration of a vendor-made MOSFET and our-developed spin-transfer-torque magnetic tunnel junction. The nonvolatile SRAM and delay flip-flop applications of PS-MOSFETs were also examined.

Original languageEnglish
Title of host publication2012 IEEE International Electron Devices Meeting, IEDM 2012
Pages29.6.1-29.6.4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States
Duration: 2012 Dec 102012 Dec 13

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2012 IEEE International Electron Devices Meeting, IEDM 2012
CountryUnited States
CitySan Francisco, CA
Period12/12/1012/12/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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    Shuto, Y., Yamamoto, S., Sukegawa, H., Wen, Z. C., Nakane, R., Mitani, S., Tanaka, M., Inomata, K., & Sugahara, S. (2012). Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices. In 2012 IEEE International Electron Devices Meeting, IEDM 2012 (pp. 29.6.1-29.6.4). [6479131] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2012.6479131