Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic

Masayuki Kawamata; Tomoo Yamakage

Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic

Masayuki Kawamata, Tomoo Yamakage

ENG - Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.

Original language	English
Pages (from-to)	735-738
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
Publication status	Published - 1990 Dec 1
Event	1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA Duration: 1990 May 1 → 1990 May 3

ASJC Scopus subject areas

Electrical and Electronic Engineering

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title = "Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic",

abstract = "A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.",

author = "Masayuki Kawamata and Tomoo Yamakage",

year = "1990",

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language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) ; Conference date: 01-05-1990 Through 03-05-1990",

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AU - Kawamata, Masayuki

AU - Yamakage, Tomoo

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Y1 - 1990/12/1

N2 - A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.

AB - A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.

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M3 - Conference article

AN - SCOPUS:0025671648

VL - 1

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

T2 - 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4)

Y2 - 1 May 1990 through 3 May 1990

ER -