Abstract
A high-speed signal processing system for 2-D state-space digital filters is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5-kb ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512 × 512. Thus, the proposed system can process television images in real time.
| Original language | English |
|---|---|
| Pages (from-to) | 735-738 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| Publication status | Published - 1990 Dec 1 |
| Event | 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA Duration: 1990 May 1 → 1990 May 3 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Kawamata, M., & Yamakage, T. (1990). Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic. Proceedings - IEEE International Symposium on Circuits and Systems, 1, 735-738.