Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation

Hiroki Abe, Hiroki Arai, Masayuki Kawamata

Research output: Contribution to journalConference articlepeer-review

Abstract

In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by adaptive algorithm based on evolutionary computation. The hardwarebased EDF version 1 consists of two submodules, that is, a filtering and fitness calculation (FFC) module and a reproduction and selection (RS) module. The FFC module has high computational ability to calculate the output and the fitness value since its submodules run in parallel. However, hardware size of the FFC module is large, and many machine cycles are needed. Thus, in the hardware-based EDF version 2, we combine the two modules to reduce its hardware size and machine cycles. A synthesis result on the FPGA shows the clock frequency is 65.5MHz and the maximum sampling rate of the hardware-based EDF version 2 is 4,948.1Hz. Moreover, the hardware-based EDF version 2 is 15.7 times faster than the hardware-based EDF version 1.

Original languageEnglish
Article number1464641
Pages (from-to)528-531
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
Publication statusPublished - 2005 Dec 1
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 2005 May 232005 May 26

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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