TY - GEN
T1 - Design and evaluation of a voltage-mode/current-mode hybrid logic circuit for a low-power fine-grain reconfigurable VLSI
AU - Bai, Xu
AU - Kameyama, Michitaka
PY - 2013/1/1
Y1 - 2013/1/1
N2 - This paper proposes a low-power two-variable logic circuit based on mixed voltage-mode/current-mode logic design. The voltage- and current-mode operations can be selected for low power consumption at low and high frequency, respectively, according to speed requirement. An nMOS pass transistor network is shared to realize voltage switching and current steering for the voltage- and current-mode operations, respectively, which leads to high utilization of the hardware resources. As a result, the power consumption of the hybrid two-variable logic circuit is lower than that of the conventional two-input look-up table (LUT) using CMOS transmission gates, when the operating frequency is more than 800 MHz. The delay and area of the hybrid two-variable logic circuit are increased by only 7% and 13%, respectively.
AB - This paper proposes a low-power two-variable logic circuit based on mixed voltage-mode/current-mode logic design. The voltage- and current-mode operations can be selected for low power consumption at low and high frequency, respectively, according to speed requirement. An nMOS pass transistor network is shared to realize voltage switching and current steering for the voltage- and current-mode operations, respectively, which leads to high utilization of the hardware resources. As a result, the power consumption of the hybrid two-variable logic circuit is lower than that of the conventional two-input look-up table (LUT) using CMOS transmission gates, when the operating frequency is more than 800 MHz. The delay and area of the hybrid two-variable logic circuit are increased by only 7% and 13%, respectively.
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U2 - 10.1109/ISOCC.2013.6864057
DO - 10.1109/ISOCC.2013.6864057
M3 - Conference contribution
AN - SCOPUS:84906903881
SN - 9781479911417
T3 - ISOCC 2013 - 2013 International SoC Design Conference
SP - 384
EP - 387
BT - ISOCC 2013 - 2013 International SoC Design Conference
PB - IEEE Computer Society
T2 - 2013 International SoC Design Conference, ISOCC 2013
Y2 - 17 November 2013 through 19 November 2013
ER -