Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA

Daisuke Suzuki, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A nonvolatile FPGA, where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, a synthesizable nonvolatile FPGA is proposed, where the circuit-configuration information is described in a hardware description language and is pushed through a standard ASIC tool flow with nonvolatile logic circuit IPs such as nonvolatile flip-flops. The use of the ASIC tool flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical design example under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, the performance of the proposed nonvolatile FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020
PublisherIEEE Computer Society
Pages194-199
Number of pages6
ISBN (Electronic)9781728154060
DOIs
Publication statusPublished - 2020 Nov
Event50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020 - Miyazaki, Japan
Duration: 2020 Nov 92020 Nov 11

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
Volume2020-November
ISSN (Print)0195-623X

Conference

Conference50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020
CountryJapan
CityMiyazaki
Period20/11/920/11/11

Keywords

  • FPGA
  • Nonvolatile logic
  • hardware description language
  • logic synthesis
  • standard-cell-based design

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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