Design and evaluation of a NULL-convention circuit based on dual-rail current-mode differential logic

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 μm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.