Abstract
A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 μm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.
Original language | English |
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Pages (from-to) | 1575-1580 |
Number of pages | 6 |
Journal | IEICE Transactions on Electronics |
Volume | E89-C |
Issue number | 11 |
DOIs | |
Publication status | Published - 2006 Nov |
Keywords
- Asynchronous logic design
- Delay insensitive
- Differential-pair circuit
- Self-timed circuit
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering