Design and evaluation of a novel real-shared cache module for high performance parallel processor chip

Zhe Liu, Jeoung Chill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi

Research output: Contribution to journalConference articlepeer-review

Abstract

Nowadays, it is very important that integrating parallel processors on a chip offers high performance and low interactive response time on applications with fine-grained parallelism and high degree of data sharing. We propose a novel real-shared cache module with new multiport ring-bus architecture to overcome the bus bottleneck problem of the existing parallel processors chip on shared cache level. A testbench of solving a large scale of simultaneous linear equation is also designed to evaluate such architecture. The evaluation results show that it can offer immediate data sharing without conflicts or delay, and the performance of parallel processors chips with such novel real-shared cache module improves in proportion to the number of processor elements.

Original languageEnglish
Pages (from-to)564-569
Number of pages6
JournalLecture Notes in Computer Science
Volume3320
Publication statusPublished - 2004 Dec 1
Event5th International Conference, PDCAT 2004 - , Singapore
Duration: 2004 Dec 82004 Dec 10

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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