Design and evaluation of a digit-parallel multiple-valued content-addressable memory

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama

Research output: Contribution to journalReview articlepeer-review

Abstract

Local and parallel communications between a memory element and a logic circuit are important advantages of content-addressable memories (CAMs) whose density and performance must be increased in various applications. The authors have already proposed a high-density multiple-valued CAM whose cell circuit is designed with only a single floating-gate MOS transistor. In this CAM, both high density and high performance are achieved because the number of access steps can be reduced to half that of a corresponding bit-serial binary CAM. In this paper, a new high-performance multiple-valued CAM is proposed to perform a digit-parallel operation, in which the number of the access steps to the CAM cells is only one. Moreover, the multistage logic circuit used to perform a one-word magnitude comparison with n digits can be designed by serial-parallel connection of one-digit comparators. As a result, a CAM one-word circuit with n digits can be designed with (2n - 1) floating-gate MOS transistors. Finally, it is demonstrated in an HSPICE simulation that under a 0.8 μm standard EEPROM design rule, the proposed digit-parallel multiple-valued CAM is much superior to a conventional binary CAM and a digit-serial multiple-valued CAM.

Original languageEnglish
Pages (from-to)48-54
Number of pages7
JournalSystems and Computers in Japan
Volume29
Issue number11
DOIs
Publication statusPublished - 1998 Oct

Keywords

  • Digit-parallel magnitude-comparison algorithm
  • Dynamic circuit
  • Floating-gate MOS transistor
  • Logic-value conversion
  • Multiple-valued threshold operation
  • Wired logic

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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