Design and evaluation of a 54 × 54-bit multiplier based on differential-pair circuitry

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

This paper presents a high-speed 54 × 54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 μm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

Original languageEnglish
Pages (from-to)683-691
Number of pages9
JournalIEICE Transactions on Electronics
VolumeE90-C
Issue number4
DOIs
Publication statusPublished - 2007 Apr

Keywords

  • Current-mode circuit
  • Differential-pair circuit
  • Multiple-valued logic

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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