Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems

Kanji Otsuka; Kanuku Ri; Mitsumasa Koyanagi

doi:10.1109/EDAPS.2013.6724448

Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems

Kanji Otsuka, Kanuku Ri, Mitsumasa Koyanagi

New Industry Creation Hatchery Center (NICHe)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

For IO interconnection, longer wiring induces larger signal delay and the driving power consumes proportionally the length of wiring. Therefore, high speed and low power IO design is definitely important for how to shorten wiring or to reduce power even relative longer wiring. Si interposer composed multi-chip (2.5D) provides more wiring space, however length of wiring would be longer than 3D-designed chip wiring. Thus, low-power IO system design must be required even in denser configuration. This paper is discussed from fundamental approach for reducing power of IO system.

Original language	English
Title of host publication	EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
Pages	25-27
Number of pages	3
DOIs	https://doi.org/10.1109/EDAPS.2013.6724448
Publication status	Published - 2013 Dec 1
Event	2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013 - Nara, Japan Duration: 2013 Dec 12 → 2013 Dec 15

Publication series

Name	EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium

Other

Other	2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
Country/Territory	Japan
City	Nara
Period	13/12/12 → 13/12/15

Keywords

IO circuit
IO for 2.5D-3D
high-speed IO

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EDAPS.2013.6724448

Cite this

Otsuka, K., Ri, K., & Koyanagi, M. (2013). Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems. In EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (pp. 25-27). [6724448] (EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium). https://doi.org/10.1109/EDAPS.2013.6724448

Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems. / Otsuka, Kanji; Ri, Kanuku; Koyanagi, Mitsumasa.

EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium. 2013. p. 25-27 6724448 (EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Otsuka, K, Ri, K & Koyanagi, M 2013, Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems. in EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium., 6724448, EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium, pp. 25-27, 2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013, Nara, Japan, 13/12/12. https://doi.org/10.1109/EDAPS.2013.6724448

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title = "Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems",

abstract = "For IO interconnection, longer wiring induces larger signal delay and the driving power consumes proportionally the length of wiring. Therefore, high speed and low power IO design is definitely important for how to shorten wiring or to reduce power even relative longer wiring. Si interposer composed multi-chip (2.5D) provides more wiring space, however length of wiring would be longer than 3D-designed chip wiring. Thus, low-power IO system design must be required even in denser configuration. This paper is discussed from fundamental approach for reducing power of IO system.",

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AB - For IO interconnection, longer wiring induces larger signal delay and the driving power consumes proportionally the length of wiring. Therefore, high speed and low power IO design is definitely important for how to shorten wiring or to reduce power even relative longer wiring. Si interposer composed multi-chip (2.5D) provides more wiring space, however length of wiring would be longer than 3D-designed chip wiring. Thus, low-power IO system design must be required even in denser configuration. This paper is discussed from fundamental approach for reducing power of IO system.

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Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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