Design and analysis of high-speed and low power Si interposer for highperformance 3D stacked systems

Kanji Otsuka, Kanuku Ri, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

For IO interconnection, longer wiring induces larger signal delay and the driving power consumes proportionally the length of wiring. Therefore, high speed and low power IO design is definitely important for how to shorten wiring or to reduce power even relative longer wiring. Si interposer composed multi-chip (2.5D) provides more wiring space, however length of wiring would be longer than 3D-designed chip wiring. Thus, low-power IO system design must be required even in denser configuration. This paper is discussed from fundamental approach for reducing power of IO system.

Original languageEnglish
Title of host publicationEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
Pages25-27
Number of pages3
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013 - Nara, Japan
Duration: 2013 Dec 122013 Dec 15

Publication series

NameEDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium

Other

Other2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
CountryJapan
CityNara
Period13/12/1213/12/15

Keywords

  • IO circuit
  • IO for 2.5D-3D
  • high-speed IO

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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