Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Toshinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masakazu Muraguchi, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical-mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically reduce memory cell area. In this paper, we first introduce the MTJ preparation technology to the mega-bit class STT-MRAM test chip, and demonstrate the improvement of memory-cell operation yield.

Original languageEnglish
Title of host publication2016 IEEE 8th International Memory Workshop, IMW 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467388313
DOIs
Publication statusPublished - 2016 Jun 15
Event8th IEEE International Memory Workshop, IMW 2016 - Paris, France
Duration: 2016 May 152016 May 18

Publication series

Name2016 IEEE 8th International Memory Workshop, IMW 2016

Other

Other8th IEEE International Memory Workshop, IMW 2016
Country/TerritoryFrance
CityParis
Period16/5/1516/5/18

Keywords

  • CMP
  • MTJ
  • STT-MRAM
  • bit yield
  • cell size

ASJC Scopus subject areas

  • Hardware and Architecture

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