Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration

Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Osada, Kenichi Takeda, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Pages175-176
Number of pages2
DOIs
Publication statusPublished - 2012
Event2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
Duration: 2012 Jun 122012 Jun 14

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2012 Symposium on VLSI Technology, VLSIT 2012
CountryUnited States
CityHonolulu, HI
Period12/6/1212/6/14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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