TY - GEN
T1 - Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration
AU - Hozawa, Kazuyuki
AU - Furuta, Futoshi
AU - Hanaoka, Yuko
AU - Aoki, Mayu
AU - Osada, Kenichi
AU - Takeda, Kenichi
AU - Lee, Kang Wook
AU - Fukushima, Takafumi
AU - Koyanagi, Mitsumasa
PY - 2012
Y1 - 2012
N2 - Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.
AB - Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections.
UR - http://www.scopus.com/inward/record.url?scp=84866546160&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84866546160&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2012.6242518
DO - 10.1109/VLSIT.2012.6242518
M3 - Conference contribution
AN - SCOPUS:84866546160
SN - 9781467308458
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 175
EP - 176
BT - 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
T2 - 2012 Symposium on VLSI Technology, VLSIT 2012
Y2 - 12 June 2012 through 14 June 2012
ER -