TY - GEN
T1 - Delay evaluation of 90nm CMOS multi-context FPGA with shift-register-type temporal communication module for large-scale circuit emulation
AU - Miyamoto, Naoto
AU - Ohmi, Tadahiro
PY - 2008/12/1
Y1 - 2008/12/1
N2 - For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circuits, each sub-circuit is assigned to a context., and the MC-FPGA sequentially executes all the contexts one by one. So, the total execution delay is the sum of the delays of the contexts. It is, therefore, said that the total execution delay of the MC-FPGA increases proportional to the number of contexts used. However, in this paper, we show that the total execution delay remains constant if a shift-register-type temporal communication module (SR-TCM) is used instead of D-FlipFlop (D-FF) to implement sequential circuits. The SR-TCM is used not only for signal communication of sequential circuit like D-FF, but also for signal communication from preceding context to succeeding contexts. In order to quantify the delay, a MC-FPGA named Flexible Processor (FP), which contains the SR-TCM, have been designed and fabricated in 90nm CMOS process technology. From the measurement results, the total execution delay of the FP was kept constant regardless of the number of contexts used.
AB - For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circuits, each sub-circuit is assigned to a context., and the MC-FPGA sequentially executes all the contexts one by one. So, the total execution delay is the sum of the delays of the contexts. It is, therefore, said that the total execution delay of the MC-FPGA increases proportional to the number of contexts used. However, in this paper, we show that the total execution delay remains constant if a shift-register-type temporal communication module (SR-TCM) is used instead of D-FlipFlop (D-FF) to implement sequential circuits. The SR-TCM is used not only for signal communication of sequential circuit like D-FF, but also for signal communication from preceding context to succeeding contexts. In order to quantify the delay, a MC-FPGA named Flexible Processor (FP), which contains the SR-TCM, have been designed and fabricated in 90nm CMOS process technology. From the measurement results, the total execution delay of the FP was kept constant regardless of the number of contexts used.
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U2 - 10.1109/FPT.2008.4762419
DO - 10.1109/FPT.2008.4762419
M3 - Conference contribution
AN - SCOPUS:63049083687
SN - 9781424427963
T3 - Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
SP - 365
EP - 368
BT - Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
T2 - 2008 International Conference on Field-Programmable Technology, ICFPT 2008
Y2 - 7 December 2008 through 10 December 2008
ER -