Degradation of memory retention characteristics in DRAM chip by Si thinning for 3-D integration

Kangwook Lee, Seiya Tanikawa, Mariappine Murugesan, Hideki Naganuma, Haro Shimamoto, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

The Young's modulus (E) of Si substrate begin to noticeably decrease below 50-μm thickness. The Young's modulus in 30-μm thick Si substrate decreased by 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si atom is highly distorted. Large distortion of the lattice structure induces the Young's modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness is bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreasing of the chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in the 20-μm thick chip is shortened by ∼40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects carrier recombination rates, consequently a shortening retention time of DRAM cell.

Original languageEnglish
Article number6531648
Pages (from-to)1038-1040
Number of pages3
JournalIEEE Electron Device Letters
Volume34
Issue number8
DOIs
Publication statusPublished - 2013 Jun 20

Keywords

  • 3-D DRAM
  • Si Young's modulus
  • mechanical strength
  • retention time

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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