Deep trench etching for through-silicon vias in three-dimensional integration technology

Jun Liang, Hirokazu Kikuchi, Takayuki Konno, Yusuke Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have developed a deep silicon trench etching process with high aspect ratio for Through-Si-Via (TSV) to fabricate high density 3-D LSIs. Here, we first etched 6-μm-thick SiO2 layer used as a passivation layer to form SiO2 trench with the depth to width ratio of 3:1 by using deep reactive ion etching (DRIE). Then, after a formation process of a fluorocarbon film for sidewall protection, we etched Si to form the Si trench with the depth to width ratio of 20:1 by inductive-coupled plasma (ICP) RIE using a time-modulation method. By employing a modified Bosch method, we formed the SiO2/Si via without side etching underneath SiO2 layer. In this paper, we investigate the effects of etching conditions on etching rate and the resulting via profile, and optimize them for complete filling of conductive materials into the SiO2/Si via. We successfully formed 2 μm TSV with a depth of more than 30 μm through a 6-μm-thick SiO 2 layer. By combining metal vertical interconnection and micro-bump technique, we developed a new 3D integration process.

Original languageEnglish
Title of host publicationSemiconductor Technology, ISTC 2008 - Proceedings of the 7th International Conference on Semiconductor Technology
Pages674-678
Number of pages5
Publication statusPublished - 2008 Sep 29
Event7th International Conference on Semiconductor Technology, ISTC 2008 - Shanghai, China
Duration: 2008 Mar 152008 Mar 17

Publication series

NameProceedings - Electrochemical Society
VolumePV 2008-1

Other

Other7th International Conference on Semiconductor Technology, ISTC 2008
CountryChina
CityShanghai
Period08/3/1508/3/17

Keywords

  • Deep Si and SiO trench etching
  • Three-dimensional integration
  • Through-silicon via (TSV)

ASJC Scopus subject areas

  • Electrochemistry

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  • Cite this

    Liang, J., Kikuchi, H., Konno, T., Yamada, Y., Fukushima, T., Tanaka, T., & Koyanagi, M. (2008). Deep trench etching for through-silicon vias in three-dimensional integration technology. In Semiconductor Technology, ISTC 2008 - Proceedings of the 7th International Conference on Semiconductor Technology (pp. 674-678). (Proceedings - Electrochemical Society; Vol. PV 2008-1).