We have developed a deep silicon trench etching process with high aspect ratio for Through-Si-Via (TSV) to fabricate high density 3-D LSIs. Here, we first etched 6-μm-thick SiO2 layer used as a passivation layer to form SiO2 trench with the depth to width ratio of 3:1 by using deep reactive ion etching (DRIE). Then, after a formation process of a fluorocarbon film for sidewall protection, we etched Si to form the Si trench with the depth to width ratio of 20:1 by inductive-coupled plasma (ICP) RIE using a time-modulation method. By employing a modified Bosch method, we formed the SiO2/Si via without side etching underneath SiO2 layer. In this paper, we investigate the effects of etching conditions on etching rate and the resulting via profile, and optimize them for complete filling of conductive materials into the SiO2/Si via. We successfully formed 2 μm TSV with a depth of more than 30 μm through a 6-μm-thick SiO 2 layer. By combining metal vertical interconnection and micro-bump technique, we developed a new 3D integration process.